Large dc motor control circuit

ABSTRACT

A motor control apparatus for starting, stopping, and regulating the speed of large electric motors.

United States Patent Inventor Appl. No.

Filed Patented Assignee Edward A. Petrocelli San Diego, Calif.

Mar. 20, 1969 Apr. 6, 1971 The United States of America as representedby the Secretary of the Navy LARGE DC MOTOR CONTROL CIRCUIT 10 Claims, 1Drawing Fig.

us. Cl 318/305, 318/411, 318/442 Int. Cl 1102p U28, 3 a 9 1 FieldofSearch 318/305,

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(an fro! References Cited UNITED STATES PATENTS Bruns Gabor DunneWasal..... Kelley Primary Examiner-Gris L. Rader AssistantExaminer-Thomas Langer Attorneys-Joseph C. Warfield, John W. Pease andJohn F.

Miller ABSTRACT: A motor control apparatus for starting, stopping, andregulating the speed of large electric motors.

mm m N Mm NW INVENTOR.

f We, BY l Patented April 6, 1971 LARGE DC MOTOR CONTROL CIRCUITSTATEMENT OF GOVERNMENT INTEREST The invention described herein may bemanufactured and used by or for the Government of the United States ofAmerica for governmental purposes without the payment of any royaltiesthereon or therefor.

BACKGROUND OF THE INVENTION The invention is in the field of motorcontrol circuits. Heretofore various devices have been utilized forstarting up and regulating the speed of large electric motors. Theinertia of the rotating elements and the lack of back electromotiveforce at low speed are such that some means of controlling the startingcurrent is necessary to avoid damage. Prior art controllers havesuffered from excessive complexity, cost and fragility. The inventionsolves this problem of the prior art by providing a rugged, simple, andinexpensive solid state circuit capable of infinite adjustment toconform to the control requirements of large DC motors.

SUMMARY OF THE INVENTION A counting chain is driven by a pulse source tocontrol a plurality of gating means which are respectively associatedwith the several stages of the chain. The gating means sequentiallyoperate selected ones of a plurality of silicon controlled rectifiers toapply selected voltages sequentially to a DC motor so as to provide anyrequired delays in the application of successively higher startingcurrents.

BRIEF DESCRIPTION OF THE DRAWING The drawing is a block diagram of theapparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawing, apulse generator 100 generates a train of pulses at a selected frequency.These pulses are supplied over a lead 102 to a three input AND gate 106and over a lead 108 to respective set-reset inputs of flip-flops 2-10and to the reset input of flip-flop I. The flip-flops 1-10 are connectedin a chain to form a counter by the unlabeled leads which connect theoutput terminal T of each flip-flop except the last one to an enablinginput E of a succeeding flipflop. For example, the output terminal T offlip-flop 1 is connected to the enabling terminal E of flip-flop 2, theoutput of 2 is connected to the enabling input of flip-flop 3, etc.Flip-flops 2-10 are so constructed that when they are in a resetcondition they will be set by a pulse on the set-reset (SR) inputterminal only if there is a voltage present on the enabling inputterminal E from a preceding flip-flop in a set condition. When one ofthe flip-flops 2-10 is in a set condition, it will be reset by a pulseon the SR input if there is no enabling voltage present. Flip-flop 1 anda control flip-flop 11 are designed to be set and reset by a pulse ontheir respective set and reset input terminals. All of the flip-flopsand other elements to be described hereinafter may be reset to aselected condition by a signal applied by conventional reset means (notshown) as is well known in the art.

The output terminal T of flip-flop 1 is also connected over a lead 1L toone input of a two input AND gate 21 and over a lead ILL to the setinput of control flip-flop 11. Flip-flop 11 when reset furnishes anoutput signal over a lead 11L to one input of three input AND gate 106.The output terminal T of flip-flop 2 also furnishes a signal over a lead2L to one input of a two input AND gate 22. In a like manner flip-flops3-10 furnish signals over leads 3L-10L to respective inputs of AND gates23-30. The respective outputs of AND gates 21- -30 are connected to aninput of respective two input OR gates 31-40. AND gates 21-30 and ORgates 31-40 each have a second input lead labeled control" whereby acontrol,

signal may be applied. The outputs of OR gates 31-40 are connected overrespective leads 3lL-40L to the respective inputs of silicon controlledrectifier (SCR) drivers 41-50.

Each driver 41-50 is connected to drive a respective silicon controlledrectifier (SCR) 51-60 to conduct current. A chain of suitable powersources shown, by way of example, as batteries 61-70 are connected inseries between one side of a large DC motor and the anode of SCR 60.Leads are connected from the respective lines between two successivebatteries in p the series connected chain to a respective anode of eachof the SCRs 51-59. For example, the anode of SCR 51 is connected to theline connecting batteries 61 and 62, SCR 52 is connected to the lineconnecting batteries 62 and 63, etc. Therefore 24 v. are applied to SCR51, since battery 61 is a 24 v. battery, 36 v. (the combined voltages of24 v. battery 61 and 12 v. battery 62) are applied to SCR 52, 48 v. areapplied to SCR 53, etc. Battery 61 is a 24 v. battery and all the otherbatteries, 62-70, are 12 v. batteries.

Motor 80 may be operated at a number of different speeds, the numberbeing determined by the number of SCRs and associated circuits in theapparatus. To start motor 80, a signal from control means (not shown) isapplied to the control leads of three input AND gate 106, to that one ofAND gates 21- -30 associated with the desired speed, and to all lowernumbered AND gates. For example, if it is desired to operate motor 80 atits fourth speed a signal would be applied to three input AND gate 106,and to two input AND gates 24, 23, 22, and 21. Since control flip-flop11 is in a reset condition, it provides a signal over line 11L to thelower input of AND gate 106. Therefore, when pulse generator nextforwards a pulse to the upper input of 106, a signal is forwarded from106 to the set terminals S of flip-flop 1.

Flip-flop 1 is so arranged and the timing of the pulses is such that thesignal to the set input prevails over the signal from pulse generator100 on line 108 applied to the reset input. Control flip-flop 11 is setby an output signal from flip-flop 1 over lines 1L and ILL whenflip-flop 1 is set. This removes the output signal from the controlflip-flop 11 furnished over line 11L to the lower input of three inputAND gate 106, thereby blocking gate 106 so that no additional pulsesfrom pulse generator 100 are passed to the set input of flip-flop 1.Flipflop 2 is enabled by the steady state output of flip-flop 1 whenflip-flop I is set, so flip-flop 2 will be set by the next pulse frompulse generator 100 on line 108. The output of flip-flop l in a setcondition is also applied to one input of two input AND gate 21. Since acontrol voltage has been applied to the other input of 21, an outputsignal from gate 21 is applied through OR gate 31 to SCR driver 41 vialine 31L. SCR driver 41 furnishes a signal to bias SCR 51 to conduct sothat SCR 51 passes current from 24 v. battery 61 through motor 80.Therefore motor 80 starts and increases its speed until it reaches itsfirst speed. The speed is determined by the 24 v. applied from 61 andthe motor characteristics. About the time that motor 80 attains itsfirst speed, pulse generator 100 applies another output pulse to the setinputs of all the flip-flops 1-10 over line 108. This has no effect onany o the flip-flops except flipflop 1 which is reset and flip-flop 2which is set due to the enabling voltage present on the output offlip-flop 1. This removes the output voltage from flip-flop l on line 1Lso that AND gate 21 is blocked. The output voltage of flip-flop 2enables flip-flop 3 to be set by the succeeding pulse on line 108 frompulse generator 100. The output of flip-flop 2 is applied over line 2Lto open AND gate 22 which has a signal voltage applied thereto on thecontrol input so that a signal is passed through OR gate 32 to SCRdriver 42 over line 32L to bias SCR 52 to conduct current from seriesconnected batteries 61 and 62 through motor 80. Motor 80 thereforeincreases its speed to step No. 2, determined by the applied 36 v. Thisvoltage back biases SCR 51 to cease conduction thus blocking thiscurrent path through SCR 51. In a similar manner, a third pulse frompulse generator 100 over line 108 will reset flipflop 2 and setflip-flop 3 which will apply a voltage over line 3L to AND gate 23 sothat SCR 53 is opened for passage of current from series connectedbatteries 61, 62, and 63 so that motor 80 accelerates to its thirdspeed. The 48 v. from series connected batteries 61, 62, and 63 backbiases SCR 52 to cease conduction thereby blocking the current paththrough SCR 52. When flip-flop 4 is set, SCR 54 opens to apply the 60 v.from series connected batteries 61l64 to motor 30 so that the motorsfourth speed is attained. The pulses from 100 are spaced at intervals oftime sufficient for motor to attain the next higher speed.

Since pulse generator 100 runs continuously the chain comprised offlip-flops 1-10 will continue to step, applying flip flop outputvoltages successively to AND gates 25--30 over lines 5L- L in the mannerdescribed. However, motor 80 does not increase its speed above thefourth speed because no signal voltages are applied to the controlinputs of AND gates 25-30.

When flip-flop chain flip-flop ll0 counts out so that all the flip-flops1-l0 are reset (control flipflop lll remains set), the pulses from pulsegenerator ltlt) on line 108 have no further effect. The system willremain in this condition until reset by applying a reset signal. Thismay be done by wellknown means, e.g., a manual switch (not shown).

Assuming that motor 80 is running at fourth speed, its speed may beincreased by applying signal voltages to higher numbered AND gatesincluding the gate associated with the desired speed and those gatesbetween the present speed and the desired speed, and to the three inputAND gate 106. For example, with motor 80 operating at its fourth speedif it were desired to increase the speed to the eighth step, a signalvoltage would be applied to the control inputs of AND gates 25, 26, 27,28, and 106.

lf motor 80 is running at a particular speed, say the eighth, and it isdesired to decrease the speed, for example, to the second speed, asignal voltage is applied to the two input AND gates associated with allthe remaining higher speeds and to the OR gate associated with thedesired lower speed and to three input AND gate 106. In the recitedexample these would be AND gates 29, 30, OR gate 32, and three input ANDgate 106. Then motor 80 will increase speed through the ninth and 10thspeeds and then drop to the second speed because of the presence of asignal voltage on OR gate 32.

If it is now desired to stop motor 80, the signal voltage is removedfrom OR gate 32 and is applied to all the two input AND gates 2ll3ll andto three input AND gate 106. Thereupon motor 80 will accelerate from thesecond speed through the successive speeds including the 10th speed andautomatically cut off.

SCRs 51-59 are selected so as to be back biased to stop conducting whenthe next higher SCR in the chain opens to apply a higher voltage tomotor 80 and to all lower numbered SCRs. Since there is no highernumbered SCR to stop conduction in SCR 60, a turn off circuit 90 isprovided to turn SCR 60 off after 60 has been conducting for a length oftime sufficient for motor 80 to accelerate from the ninth to the 10thspeed.

The components shown in the drawing are all well known in the art andwill not be described in detail. The particular pulse generator, gates,flip-flops, etc. are chosen to serve the par ticular application.Flip-flops may be selected with switching times suitable for aparticular motor. A single flip-flop of the chain 1-10 is shown locatedbetween the leads to successive two input AND gates by way of exampleonly. This merely illustrates that a delay occurs between switching on ahigher voltage to increase the speed of motor 80. The inventioncontemplates the use of flip-flops with various switching times and/or aplurality of flip-flops in a chain between a pair of adjacent AND gateleads in order to tailor the invention to the requirements of aparticular motor. For example, if more delay were required between oneor more steps, two or more flip-flops could be connected between two ANDgate inputs so that two or more pulses from 106 would be counted beforemotor 80 was switched to a higher speed. SCR turn off circuit 90 may beany circuit which will back bias SCR 60 to cut 01? after a suitabledelay. For example, circuit 90 can comprise a suitable capacitor and aresistor connected in parallel in the cathode circuit of SCR as. WhenSCR 6t) conducts, a voltage will build up on the capacitor which aftersome delay is sufficient to cut off the SCR. The capacitor may bedischarged by a suitable transistor 01' other switch means connectedacross the capacitor. This may be actuated to discharge the capacitor bythe conventional reset means employed to reset the flip-flops of theinvention, if desired. SCRs 51-60 are selected to match the voltagesources to which they are respectively connected. The term flip-flop isemployed for convenience of description, but is not limited to aconventional bistable multivibrator. It is intended to include anysuitable two-state device, particularly in the counting chain, where asingle tube, transistor, or equivalent two-state device may suffice fora stage.

lclaim:

1. In a motor control circuit, the improvement comprising: a motor, aplurality of voltage sources connected to provide a plurality ofsuccessively higher voltages, a plurality of selectively actuated switchmeans arranged to selectively connect respective ones of said voltagesources to said motor in a selected sequence, a plurality of drivermeans for driving said switch means, a cascaded chain of two statedevices, pulse generator means arranged to supply a train of pulses tosaid cascaded chain of two state devices to sequentially switch said twostate devices, a plurality of gating means, and means connecting saidcascaded chain of two state devices, said plurality of gating means,said driver means, and said switch means whereby said two state devicescontrol the actuation of said switch means to connect said voltagesources to said motor in a selected sequence.

2. The apparatus of claim 1 wherein said gating means are provided withcontrol leads whereby control signals may be applied to selected ones ofsaid gating means to thereby determine said selected sequence.

3. The apparatus of claim 2 wherein said gating means comprise aplurality of two input AND gates and a like plurality of OR gates, eachof said two input AND gates having an output connection to the input ofa respective one of said OR gates.

4. The apparatus of claim 3 wherein said control leads comprise aplurality of control leads with a control lead connected to the input ofeach respective one of said AND gates whereby selected ones of said ANDgates may be enabled to pass a signal from a respective one of said twostate devices to the input of a respective one of said OR gates, andwhereby selected ones of said OR gates may be selectively enabled by acontrol signal applied to its control lead.

5. The apparatus of claim 4 and including control means for controllingthe supply of said train of pulses from said pulse generator means tosaid cascaded chain of two state devices.

6. The apparatus of claim 5 wherein said control means comprise a threeinput AND gate, and a control flip-flop, one input of said three inputAND gate being connected to the output of said pulse generator means, asecond input of said three input AND gate being connected to the outputof said control flip-flop, the third input of said three input AND gatebeing adapted to receive a control signal, the output of said threeinput AND gate being connected to the set input of said first of saidtwo state devices, whereby when a control signal is applied to saidthree input AND gate said gate is enabled to pass a pulse from saidpulse generator means to set said first two state device.

7. The apparatus of claim 6 and including means connecting the output ofsaid first one of said two state devices to the set input of saidcontrol flip-flop to set said control flip-flop and thereby remove theoutput voltage of said control flip-flop from said second input of saidthree input AND gate to thereby close said three input AND gate to thepassage of pulses from said pulse generator means.

8. The apparatus of claim 7 wherein the output of each of said two statedevices is connected to an enabling input of the next succeeding twostate device to enable said succeeding two state device to be set by apulse on its set-reset input from said pulse generator means.

9. The apparatus of claim 8 wherein said connecting means comprise aconnection from the output of each of said two whereby a rectifieractuated to connect a voltage source to said motor is deactuated when arectifier connecting a higher voltage source to said motor is actuated.

1. In a motor control circuit, the improvement comprising: a motor, aplurality of voltage sources connected to provide a plurality ofsuccessively higher voltages, a plurality of selectively actuated switchmeans arranged to selectively connect respective ones of said voltagesources to said motor in a selected sequence, a plurality of drivermeans for driving said switch means, a cascaded chain of two statedevices, pulse generator means arranged to supply a train of pulses tosaid cascaded chain of two state devices to sequentially switch said twostate devices, a plurality of gating means, and means connecting saidcascaded chain of two state devices, said plurality of gating means,said driver means, and said switch means whereby said two state devicescontrol the actuation of said switch means to connect said voltagesources to said motor in a selected sequence.
 2. The apparatus of claim1 wherein said gating means are provided with control leads wherebycontrol signals may be applied to selected ones of said gating means tothereby determine said selected sequence.
 3. The apparatus of claim 2wherein said gating means comprise a plurality of two input AND gatesand a like plurality of OR gates, each of said two input AND gateshaving an output connection to the input of a respective one of said ORgates.
 4. The apparatus of claim 3 wherein said control leads comprise aplurality of control leads with a control lead connected to the input ofeach respective one of said AND gates whereby selected ones of said ANDgates may be enabled to pass a signal from a respective one of said twostate devices to the input of a respective one of said OR Gates, andwhereby selected ones of said OR gates may be selectively enabled by acontrol signal applied to its control lead.
 5. The apparatus of claim 4and including control means for controlling the supply of said train ofpulses from said pulse generator means to said cascaded chain of twostate devices.
 6. The apparatus of claim 5 wherein said control meanscomprise a three input AND gate, and a control flip-flop, one input ofsaid three input AND gate being connected to the output of said pulsegenerator means, a second input of said three input AND gate beingconnected to the output of said control flip-flop, the third input ofsaid three input AND gate being adapted to receive a control signal, theoutput of said three input AND gate being connected to the set input ofsaid first of said two state devices, whereby when a control signal isapplied to said three input AND gate said gate is enabled to pass apulse from said pulse generator means to set said first two statedevice.
 7. The apparatus of claim 6 and including means connecting theoutput of said first one of said two state devices to the set input ofsaid control flip-flop to set said control flip-flop and thereby removethe output voltage of said control flip-flop from said second input ofsaid three input AND gate to thereby close said three input AND gate tothe passage of pulses from said pulse generator means.
 8. The apparatusof claim 7 wherein the output of each of said two state devices isconnected to an enabling input of the next succeeding two state deviceto enable said succeeding two state device to be set by a pulse on itsset-reset input from said pulse generator means.
 9. The apparatus ofclaim 8 wherein said connecting means comprise a connection from theoutput of each of said two state devices to one input of a respectiveone of said two input AND gates.
 10. The apparatus of claim 9 whereinsaid switch means are silicon controlled rectifiers, means connectingsaid rectifiers whereby a rectifier actuated to connect a voltage sourceto said motor is deactuated when a rectifier connecting a higher voltagesource to said motor is actuated.